This invention relates to an engagement detection circuit for detecting and indicating the engagement condition of a phase control circuit, with a phase detector, a counter element and a flip-flop. In the invention, the phase detector is acted upon on the input side by a data signal and a clock pulse and controls on the output side the counter element, and whereby the flip-flop, connected to the output of the counter element, is set or reset depending on the counter reading.
Furthermore, the invention relates to a clock recovery circuit that operates with such an engagement detection circuit.
Data communication over long transmission distances is increasingly gaining importance. Especially in connection with long traffic distances, the glass fiber optic transmission technology is becoming more and more successful because of the very high data transmission rates realizable with fiber optic lines. In the field of data transmission via glass fiber optic lines, the quality of the signal deteriorates due to fiber damping, signal distortions and noise. The signal therefore has to be regenerated repeatedly. This is accomplished by means of optical amplifiers and special optoelectronic regenerators. While only the fiber damping can be compensated by means of optical amplification, the optoelectronic regenerators permit almost complete regeneration of the data signal. So-called clock recovery circuits are the central components of such regenerators. Such recovery circuits serve to extract a low-noise clock pulse from the distorted and high-noise data signal. The data signal is then scanned in the regenerator with the recovered clock pulse and almost complete regeneration is achieved in that way. The clock recovery circuit operates completely electronically, which is why electrooptical signal conversions are required with the optoelectronic regenerator on the input and output sides. The so-called PLL""s, or phase-locked control loops are advantageously employed for the clock recovery. These control loops consist of a phase detector on the input side, a loop filter, and a voltage-controlled oscillator on the output side, with a feedback of the output of the oscillator to the input of the phase detector. The phase control loop extracts the clock pulse from the data signal by controlling the voltage-controlled oscillator so that it oscillates synchronously with the data signal. The phase detector supplies the loop filter with a control signal that corresponds with the phase difference between the data signal and the output signal. The signal is low-pass filtered in the loop filter and controls the frequency of the voltage-controlled oscillator. Furthermore, phase control loops are very well-suited for bit rate-flexible clock recovery, wherein the frequency is adjusted not only by mistuning the voltage-controlled oscillator, but also by means of a frequency division. Clock recovery circuits can be realized in this manner in a very simple way that can be employed for all commonly used bit rates. An engagement detection circuit is required in this connection for automatically detecting and selecting the bit rate. By means of such an engagement detection circuit, it is possible to realize a control circuit that controls the oscillator frequency and the frequency division ratio. A bit rate range is selected by means of the switchable frequency divider, whereas safe locking to the desired bit rate can take place by means of the phase control loop. Clock recovery circuits with a bit rate range comprising several decimal powers can be realized in that way.
An engagement detection circuit of the type specified above is described, for example in U.S. Pat. No. 5,905,410. This known circuit indicates the engagement or disengagement of a phase control loop. This known circuit uses the output signal of the phase detector that determines the phase difference between the clock pulse of the phase control loop and the data signal. By means of a suitable digital circuit, the output signal of the phase detector is used for resetting at a time, one of two separate counters. One of the two counters is responsible for the clock cycles that are in phase, and the other for the cycles that are out of phase. Both counters are synchronously incremented by means of the clock pulse. The counter for the clock cycles that are in phase, has a higher bit number than the counter for the cycles that are out of phase. The overflows of the two counters are connected to the setting and resetting inputs of a flip-flop; the condition of the latter indicates the engagement of the phase control loop. What is achieved is that any engagement is signalized only after a high number of in phase clock cycles, whereas just a few clock cycles that are out of phase are sufficient for indicating any disengagement. The drawback of this known engagement detection circuit is that an unsolvable conflict of objectives exists between the rapid detection of engagement and disengagement that is desirable on the one hand, and resists unavoidable signal errors such as noise that is required on the other hand. Using the known engagement detection circuit in clock recovery circuits has the drawback that the speed of the frequency search is limited by the time constant of the engagement detection.
The present invention provides an engagement detection circuit where the aforementioned drawbacks are avoided to the greatest possible extent, and whereby it is particularly possible to realize rapid, yet noise-proof engagement detection. It is therefore possible to realize clock recovery circuits with rapid frequency detuning where the speed of the frequency search is not limited by the time constant of the engagement detection.
This problem is solved with an engagement detection circuit of the type specified above, in that a low-pass element and a trigger element are connected downstream of the flip-flop.
With the circuit of the invention, two different engagement signals are generated. The flip-flop indicates an engagement with low time delay. This preliminary engagement signal, however, has at the same time, a high sensitivity to noise influences. The first engagement signal serves as input for a low-pass element, to which a trigger element is connected downstream according to the invention. If the preliminary engagement signal is applied over a time that is preset by the time constant of the low-pass element, the trigger element is activated, and indicates at its output, a final engagement of the phase control loop with comparatively high time delay versus the preliminary engagement signal, whereby the final engagement signal however, has only a low sensitivity to noise disturbances.
An important advantage of the invention is that a high frequency detuning speed and thus a rapid frequency acquisition by the clock recovery circuit are possible due to the short time constant of the preliminary engagement detection. With a clock recovery circuit, the final engagement indication can be used at the time for preventing disengagement, because of short-time signal disturbances and noise. With a clock recovery circuit, the engagement behavior and the frequency acquisition behavior become independent of one another in this way.
It is useful to employ as the phase detector, a quadrature phase detector in connection with the engagement detection circuit with the data signal and the quadrature clock pulsexe2x80x94the latter being shifted by 90xc2x0xe2x80x94being applied to the input of the quadrature phase detector. The phase detector then generates output signals that are dependent only on the sign of the phase difference between the data signal and the clock pulse. The output signals can be usefully employed for controlling an incrementer/decrementer. In the engagement detection circuit of the invention, the incrementer/decrementer is employed as the counter element. It is then advantageously possible to control the incrementer/decrementer via the phase detector so that the incrementing or the decrementing input is activated depending on the phase difference between the data signal and the clock pulse. An incrementing count, for example, can then always take place when a positive phase difference is present between the date signal and the clock pulse. A decrementing count takes place in the presence of a negative phase difference. If, in the presence of an adequate number of clock cycles, the phase difference has a positive sign, the incrementing/decrementing counter is incremented until the overflow threshold has been reached. The flip-flop connected to the overflow of the counter element is then activated and, according to the invention, indicates the preliminary engagement. It is useful in this connection if the incrementing or decrementing count takes place with different incrementation, whereby the decrement is greater than the increment because phase differences with positive and negative signs will then occur with about the same frequency in the disengaged condition. Due to the fact that the decrement is greater than the increment, the counter element of the invention is safely decremented up to a minimum value. The flip-flop is usefully controlled so that it is reset when a defined counter reading is not reached, so that the output of the flip-flop indicates complete disengagement. Tests have shown that the engagement detection circuit of the invention operates in a particularly reliable way if the ratio of the decrement to the increment has a value of smaller than or equal to 3:1.
The flip-flop is advantageously controlled by the output of the counter element via an interconnected logic element. The individual bits of the counter element can then be linked so that any desired threshold value can be preset for resetting the flip-flop when the threshold value is not reached.
The low-pass element connected of the invention, downstream of the flip-flop, may be a conventional, analog operating low-pass filter. A common Schmitt trigger can be employed as the trigger element. As an alternative, it is advantageously possible to replace these elements by components that completely operate digitally. It is advantageous to use a counter element as the low-pass element, and to employ as the trigger element, a logic element and flip-flop combination. The digital solution offers the advantage that the time constant of the low-pass element can be adapted to the frequency if, for example, the additional counter element is incremented via the clock pulse.
With the engagement detection circuit as defined by the invention, it is possible to realize a particularly efficient clock recovery circuit. This clock recovery circuit has a phase control loop with a phase detector, a loop filter, a voltage-controlled oscillator, and a controllable frequency divider, whereby the voltage controlled oscillator and the frequency divider are controlled by means of a control circuit, depending upon the output signals of the engagement detection circuit. The engagement detection circuit as defined by the invention is combined in this connection with a conventional phase control circuit whose frequency can be tuned through continuously, and with a special control circuit. The control circuit controls the frequency detuning of the voltage-controlled oscillator and at the same time the frequency division ratio of the switchable frequency divider, in dependence of the preliminary and the final engagement detection. The oscillator may be detuned from its minimum up to its maximum oscillation frequency, which can be accomplished, for example by controlling the voltage of the loop filter. The various frequency bands are selected with the switchable divider.
With the clock recovery circuit as defined by the invention, it is useful if the bandwidth of the loop filter is controlled by means of the control circuit as well. A wide-banded filter characteristic of the loop filter is required for a rapid frequency search. For the final, exact engagement, it is then possible to reverse to a narrow-band characteristic.